Driven by the increasing size and complexity of digital designs, there has been a renewed interest in high level synthesis of digital circuits from behavioral descriptions both in the industry and in academia. A key change that has taken place since high-level synthesis was first explored two decades ago is the widespread acceptance and use of register-transfer level (RTL) language modeling of digital designs. In fact, recent years have seen the use of variants of programming languages such as “C” and “C++” for behavioral level modeling. High-level synthesis and verification tools are essential for enabling widespread industrial adoption of these system-level programming paradigms.
However, there are several challenges that limit the utility and wider acceptance of high-level synthesis. There is a loss of control on the size and quality of the synthesized result. High-level languages allow for additional freedom in the way a behavior is described compared to register-transfer level descriptions. Thus, the style of high-level programming, in particular, the overall control flow and choice of control flow constructs, often has an unpredictable impact on the final circuit. Thus, we need techniques and tools that achieve the best code optimizations and synthesis results irrespective of the programming style used in the high level descriptions.